Switching Activity Reduction Technique In Soc Testing
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 12
Abstract
This paper discusses the generation Pseudo Random number generation using Low Power Linear Feedback Shift Resister (LFSR) which is more suitable for Built-In-Test (BIT) structures used for testing of VLSI circuits. BIT is a design for testability (DFT) technique in which testing is carried out using built in hardware features. Since testing is built into the hardware, it is faster and efficient. The proposed test pattern generator reduces the switching activity among the test patterns.
Authors and Affiliations
P. Sai Kumar| M.Tech Scholor Vlsi Design, N. S. Govind| Asst. Professor H.O.D (E.C.E)
Keywords
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