0.18µm CMOS Based Divider for Wireless Applications Using Wideband Prescalar
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 10
Abstract
Wireless LAN (WLAN) in the multigigahertz bands, such as HiperLAN II and IEEE 802.11a/b/g, are recognized as leading standards for high-rate data transmissions and standards like IEEE 802.15.4 are recognized for low-rate data transmissions. The demand for lower cost, lower power and multiband RF circuits increased in conjunction with need of higher level of integration. The frequency synthesizer, usually implemented by a phase-locked loop (PLL), is one of the power-hungry blocks in the RF front-end and the first-stage frequency divider consumes a large portion of power in a frequency synthesizer. In this paper, a wideband 2/3 prescaler is verified in the design of proposed wide band and multimodulus 32/33/47/48 prescaler. A dynamic logic multiband flexible integer-N divider is designed which uses the wideband 2/3 prescaler, multimodulus 32/33/47/48 prescaler. However, the P and S counters are programmed accordingly. From the synthesis report the minimum period and the maximum frequency required to maintain the functionality are 3.606ns and 277.316MHz.The proposed design consumes the power dynamically according to the corresponding selected FPGA.
Authors and Affiliations
Sunitha Kalluri, P. Bala Murali Krishna
Keywords
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