3-D Field Programmable Gate Interconnect Faults by Testing and Diagnosis

Abstract

The emerging three-dimensional (3D) integration technology is one of the promising solutions to overcome the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. As the fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques are imperative for the successful adoption of 3D integration technology. A brief introduction on the 3D integration technology has been proposed, and then reviewed the EDA challenges and solutions that can enable the adoption of 3D ICs, and finally presented the design and architectural techniques on the application of 3D ICs, including a survey of various approaches to design future 3D ICs, leveraging the benefits of fast latency, higher bandwidth, and heterogeneous integration capability that are offered by 3D technology.

Authors and Affiliations

Velpuri Jagathi

Keywords

Related Articles

Non Linear Transient Thermal Analysis of Turbine Blade Cooling

The main objective of this paper is to reduce the turbine blade high temperature gases from combustion chamber. Because of this temperature the life of the blade is going to get decrease significantly. It is necessary t...

Network Load Balancing Using Distributed Algorithm

Network Load Balancing (NLB) is a clustering technology offered by Microsoft as part of all Windows 2000 Server and Windows Server 2003 family operating systems. NLB uses a distributed algorithm to load balance network...

National Scheduled Tribes Finance and Development Corporation and its Impact on Tribal Community Development in India

This paper focused on tribal community development through National Scheduled Tribes Finance and Development Corporation (NSTFDC) is provides skill development awareness programmes, financial helps to tribal community d...

Design & Implementation Of On Chip Permutation Network for MPSOC on FPGA

This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switchin...

slugWireless Base Station With Reduced Crest Factor

In this paper computationally efficient signal shaping strategy is developed that can be used to substantially reduce the PAPR in multiband transmitters. In this report, we provide mathematical framework for design and...

Download PDF file
  • EP ID EP19990
  • DOI -
  • Views 261
  • Downloads 4

How To Cite

Velpuri Jagathi (2015). 3-D Field Programmable Gate Interconnect Faults by Testing and Diagnosis. International Journal for Research in Applied Science and Engineering Technology (IJRASET), 3(3), -. https://europub.co.uk/articles/-A-19990