64 Bit Domino Logic Adder with 180nm CMOS Technology
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 4
Abstract
Based on 180nm CMOS technology a 64 bit domino logic adder is designed for energy and speed optimization. The adder is designed using 4 bit slice of carry look-ahead adder. Multiple slices are connected in ripple carry fashion to obtain 64 bit adder. This result in considerable reduction in time as compared to nominal ripple carry adder. Implementation of equations of sum, generate and propagate are implemented in domino CMOS logic using TSMC 180nm library to provide energy optimization. The latency is no more than 33 clocks with a transistor count of 1504. Average power results are also presented in this paper with selected input vectors. average power for the design is calculated over the transient analysis. The simulation report from the TannerTool T-spice gives the following result after complete simulation, average power is 4.65 microwatt.
Authors and Affiliations
M. B. Damle, , Dr. S. S. Limaye,
Keywords
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