A 4-Dimensional Parity based Data Decoding Scheme for EDAC in Communication Systems
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 4
Abstract
The applications and use of hardware in wireless communication is increasing day by day. Portability of systems with data integrity during communication is the basic need of the systems in communication technology. This is a great force for the development of low power systems architectures. The wireless communication medium has various signals that can affect the low power communication signals of any system. So in wireless systems that operate on low power signals a good technique of data encoding and decoding is always preferred to use to transmit data through the medium. An effective data decoder is capable of identifying the changes that are caused in the transmitted data in the communication path and also capable to correct the data. Such an encoding-decoding technique is called as Error Detection and Correction (EDAC) Coding Technique. One of such technique that is most commonly used in the communication systems is based on the concept of Parity Encoding and Decoding. In the proposed work a 4-dimensional parity based encoding-decoding algorithm is presented. In this algorithm the error detection and correction logic is implemented by calculating parity of a data set in a matrix arrangement. The parity is calculated in the directions: horizontal, vertical, forward diagonal and backward diagonal. This algorithm is a low-complex hardware implementation design of error detection and correction code. The present work presents the hardware resource utilization on Xilinx FPGA devices.
Authors and Affiliations
Vijay Tawar, Rajani Gupta
Keywords
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