A Brief Review of SRAM Architecture with Various Low leakage Power Reduction Technique in Recent CMOS Circuit
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 1
Abstract
In the integrated circuits that have memories, a major share of total circuit power is required by the memory architecture of the circuit. With the day-to-day changing circuit designs, the need to store increasing amount of processing data has resulted in the growing memory size in an integrated circuit. Most of the memory data remains unaltered during the memory data handling operation. The stored data is thus affected by the sub-threshold leakage power / current that leads to the degradation of data signal quality. The data integrity is maintained using a feedback path / architecture in SRAM memory architecture. Still, the amount of power loss due to leakage contributes a major part of the total power loss of the integrated circuit. This loss increases with the decrease in the physical feature size of the component / transistors. A low power system offers the benefits like device portability, long battery life, good performance criteria, etc. Today’s increasing data handling require more random access memory to process the dynamic data. In memories and also in processing and data handling operations low power dissipation is desired from the operational circuits. This survey paper use the design of SRAM architecture to reduce the leakage current and hence the leakage power. The various leakage power reduction techniques have been evolved to tackle the problem and it is still in progress. In this paper mainly, the study of various leakage power reduction technique with SRAM architecture in fab Technology. In this review paper latest work done on a new technique called LECTOR (Leakage Control Transistor Technique) is explained here.
Authors and Affiliations
Sonam Rathore, Vijay Yadav, Dr. Rita Jain
Keywords
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