Abstract

: With the increasing applications of electronics in day-2-day life and alteration in design techniques in the field of VLSI, we are required to design the ICs with maximum efficiency. By efficiency, here we mean the power consumption, the delays, operation at different frequencies and the stability of designed circuit. In this paper we have focused on the Clock Gating technique to decrease the dynamic power dissipation of CMOS based circuit, being an issue of great concern at higher clock rates. Further we analyzed a Clock Gating technique to observe difference in the power consumption in Johnson Counter. Doing some power analysis in SPICE, it is observed that proposed technique has lower power dissipation compared to the conventional design.

Authors and Affiliations