A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL

Journal Title: INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY - Year 2014, Vol 13, Issue 2

Abstract

There is a definite need for video and image processing technologies in today's world. However the computer vision technologies need to be tested and optimized. There is need for testing these interfaces for the platform which we work on. This modeling is a cost effective architecture for interfacing Digital Visual Interface(DVI) on Virtex5 FPGA's. The architecture is modeled in such a way that it does not use XPS micro blaze or Power PC  processor but simple pixel feeder design, configuration of the Chrontel 7301C chip design and the interface between them.

Authors and Affiliations

Asif Ahmad A S

Keywords

Related Articles

History Aware Anomaly Based IDS for Cloud IaaS

Cloud Computing provides different types of services  such as SaaS, PaaS, IaaS. Each of them have their own security challenges, but IaaS undertakes all types of challenges viz., network attack ,behaviour based attack,...

A SIGNATURE IDENTIFICATION SYSTEM WITH PRINCIPAL COMPONENT ANALYSIS AND STENTIFORD THINNING ALGORITHMS

Several biometric security systems have been implemented. Biometric is the use of a person’s physiological or behavioural characteristics to identify the individual. An example of behavioural method of biometric is sig...

Shape Matching and Recognition using Hybrid Features from Skeleton and Boundary

This paper presents a novel approach for effective matching of similar shapes from skeleton and boundary features. The features identified from the shape are the junction points, end points, and maximum length from singl...

A Seismic Data Processing System based on Fast Distributed File System

Big data has attracted an increasingly number of attentions with the advent of the cloud era, and in the field of seismic exploration, the amount of data created by seismic exploration has also experienced an incredible...

Power Saving Management in Ad-Hoc Wireless Network

In wireless network Power Saving is an important issue. In this work power savingis done via a sequence of procedures. Power Saving (PS) function describes the necessary steps for a station in PS mode to turnoff the tran...

Download PDF file
  • EP ID EP650525
  • DOI 10.24297/ijct.v13i2.2905
  • Views 87
  • Downloads 0

How To Cite

Asif Ahmad A S (2014). A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL. INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY, 13(2), 4230-4236. https://europub.co.uk/articles/-A-650525