A High Speed Vedic Multiplier Using Different Compressors
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 11
Abstract
A digital clock rate multiplier, divisor using variable point math which generates the output clock with almost zero occurrence error has been presented. The circuit has an uncontrolled multiplication and division factor range and short lock time. A short power method has been incorporated to ensure that the overall power consumption of the circuit is low. The circuit has been premeditated in TSMC 65nm CMOS process for an input allusion time of 0.01ns and has been tested with indiscriminate multiplication factor values, we present a novel architecture to perform high speed multiplication using ancient Vedic math’s techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been discovered. Upon evaluation, the compressor based multiplier introduced in this paper, is nearly two times faster than the popular methods of multiplication. With regards to area, a 1% diminution is seen. The design and tests were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the similar have been calculated.
Authors and Affiliations
D. D. Devi Sasikala| Associate professor, Department of ECE, Sri Venkateswara Engineering And Technology, Chittor, N. V. Nagaraju| Student Department of ECE, Sri Venkateswara Engineering And Technology, Chittor
Keywords
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