A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2017, Vol 8, Issue 2
Abstract
Over many years, Field Programmable Gated Ar-rays (FPGA) have been used as a target device for various prototyping and cryptographic algorithm applications. Due to the parallel architecture of FPGAs, the flexibility of cryptographic algorithms can be exploited to achieve high throughputs at the expense of very low chip area. In this research, we propose a low cost FPGA based cryptosystem named as Secure Cipher for high throughput to area ratio. The proposed Secure Cipher is implemented using full loop unroll technique in order to exploit the parallelism of the proposed algorithm. The proposed cryp-tosystem implementation achieved a throughput of 4600Mbps for encryption. The logic resource utilization of this implementation is 802 logic elements(LE) which yields a throughput to area ratio of 5.735Mbps/LE.
Authors and Affiliations
Muhammad Sohail Ibrahim, Irfan Ahmed, M. Imran Aslam, Muhammad Ghazaal, Kamran Raza, Shujaat Khan
Keywords
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- EP ID EP249343
- DOI 10.14569/IJACSA.2017.080249
- Views 82
- Downloads 0
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