A Low Power 4 Bit Successive Approximation Analog-To-Digital Converter Using 180nm Technology
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 6
Abstract
In this paper, 4 bit successive approximation analog-to- digital converter (SAR ADC) has been designed. The design is using Cadence tool with 180nm CMOS technology in which supply voltage is 3.3V. The successive approximation has three components which are comparator, control logic and digital- to- analog converter.The SAR ADC is used widely in data acquisition techniques at the sampling rates higher than 10KHz like computer, microcontroller, microprocessor, TV etc. Simulation result shows that proposed successive approximation analog-to-digital converter have a power efficiency or consumption of 3.323mwatt.
Authors and Affiliations
Jasbir Kaur, Praveen Kumar
Keywords
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