Abstract

Data transmission is the physical transfer of data over the communication channel. Error correcting coding has become one of the essential part in the modern data transmission and storage systems. During transmission, there is a chance of error affecting on channel. So the error correction codes are used to reduces the number of errors in the channel. Various error correction codes can be used to detect and correct the errors. Low Density Parity Check (LDPC) codes are a class of linear block codes, has the superior performance in error detection and correction. This method presents an error detection and correction method using Euclidean Geometry Low Density Parity Check codes (EG-LDPC) with majority logic decoding. EG-LDPC codes are the class of Low Density Parity Check codes for detecting and correcting the errors. It is based on the bit flipping algorithm. The bit flipping algorithm utilizes the check sum equations in order to detect and correct the errors. The VHDL language is used for coding. Synthesis is done in Xilinx ISE design suite 13.2 and ModelSim 6.3f is used for simulation.

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