A New VLSI Architecture to Increase the speed of computation (Modified Booth Algorithm)
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 9
Abstract
In this paper, we planned a new architecture of multiplier -and-accumulator (MAC) for high-speed arithmetic operations. By merging multiplication with accumulation and planning a hybrid type of carry save adder (CSA), the performance was better. Since the accumulator that has the major delay in MAC was merged into CSA, the total performance was raised. The proposed CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and creates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it likely to optimize the pipeline scheme to improve the performance. In this work, for simulation we use Modelsim for logical verification, and further synthesizing it on XilinxISE tool using target technology and performing placing & routing operation for system confirmation on targeted FPGA. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.
Authors and Affiliations
CH. Rama Koti Reddy, K. Satyavathi, R. Raja Kishore
Keywords
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