A Novel AHB Based SDRAM Memory Controller
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 6
Abstract
This paper describes design of the memory controller which is compatible with Advanced High-performance Bus (AHB), which is a new generation of AMBA bus. The AHB is mainly meant for high-performance and high clock frequency system modules. The Memory Controller using FIFO provides command signals for memory refresh, read & write operations and initialization of SDRAM. Our work will focus on SDRAM Controller that is located between the SDRAM and AHB interface. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle.
Authors and Affiliations
P. Himabindu, G. M. V. Prasad, A. Srinivas Rao
Keywords
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