A Novel Design of Low Power Comparator through Differential Amplifier in 90nm CMOS Technology Using Cadence Tool
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 6
Abstract
In digital world, Speed, area, power are very vital parameters for high speed devices like analog to digital converters. The comparator circuit with preamplifier increases the power consumption, as it requires large amount of currents than the latch circuitry. In this paper, a novel design of low power comparator is explained, which is able to provide high speed, and the low power using cross coupled differential amplifier in the latch stage in 90nm CMOS technology. The comparator is designed using cadence tool with 1.2 V DC power supply in 90nm CMOS technology. The power consumption of the proposed comparator is 0.8121uW which is very convenient for making high speed devices.
Authors and Affiliations
Rahul D. Marotkar, Dr. Manoj S. Nagmode
Keywords
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- EP ID EP21002
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