A Novel Energy Efficient Transmission gate Voltage Level Shifter for multi VDD systems
Journal Title: International Journal of Scientific Research and Management - Year 2015, Vol 3, Issue 3
Abstract
A new design of level - up and level - down shifter for low - power and high speed applications has been presented. Level - up and level - down operations can be perform by using the new well - organized Transmission gate Voltage Level Shifter (TVLS). In this paper a novel voltage level shifter h ave introduced that performs level - up shift or level - down shifts. In this, the circuit watch its input logic voltages and perform leve - up shift, when its input voltage is low and level - down shift when its input voltage is high. This TVLS constantly perform s level - up shift from 0.4V to 1V and level - down shift from 1V to 0.4V. The schematic design has been design and simulated using 90nm CMOS process technology. In analysis of power and delay, TVLS has level - up and level - down average power consumption is 24. 7145nW and with a propagation delay of 2.053ns has obtained at 1 MHz .
Authors and Affiliations
Padmapriya K esari
Keywords
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