A Novel Method for Diagnosis of Faults Caused At Multiple Locations
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 2
Abstract
Testing is an important early step in design of VLSI. With tens of billions of transistors being integrated in one chip, multiple faults may exist. To accurately and efficiently identify the fault locations, a cube-based EPP analysis technique is proposed. The calculated percentage represents the EPP of the injected fault. In the circuit, the cube values of location at the initial stages are altered and the error count is calculated. This is done until the error count reduces to zero. Both the techniques are applied to ISCAS ’89 benchmark circuits and the parameters such as area, speed and power are computed. It can be observed that the area and power are reduced remarkably by EPP method compared to FEG method and the speed increases approximately by 7 times. The results show that the EPP method is more advantageous than the graph-based approach.
Authors and Affiliations
T. C. Sabareeswari, A. J. G. Angeline Monica
Keywords
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