A Novel Multiplier Design Using Adaptive Hold Logic to Mitigate BTI Effect
Journal Title: GRD Journal for Engineering - Year 2016, Vol 1, Issue 0
Abstract
The overall performance of a system depends on the performance of the multipliers, thus digital multipliers are among the most critical arithmetic functional units; but their performance is affected by negative bias temperature instability effect and positive bias temperature instability effect. The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs =−Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both these effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore this paper proposes an aging-aware multiplier design with a new adaptive hold logic (AHL) circuit. To mitigate performance degradation due to the aging effect, this architecture can be applied to a column- bypassing multiplier or row-bypassing multiplier.
Authors and Affiliations
A. Gopivignesh, P. N. Sundararajan
Keywords
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