A Static Time Analysis of 1-bit to 32-page SCA architecture for Logic Test
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2013, Vol 1, Issue 7
Abstract
This research proposes the Static Time Analysis of 32 page Single cycle access (SCA) architecture for Logic test. The timing analysis of each and very path of Logic test are observed that is setup and hold timings are calculated. It also eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles using ClockGating technique. This leads to more realistic circuit behavior during at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycle per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. The structure allows an additional onchip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self-test (BIST) and massive parallel scan chains. The results are observed on Xilinx XC3s1600e-5fgg484
Authors and Affiliations
K. Surya Kumari| Asst.Prof, Dept of ECE, M Tech Scholar,Asst.Prof, Dept of ECE Pragati Engg College, Surampalem, Sneha. M. Joseph| Asst.Prof, Dept of ECE, M Tech Scholar,Asst.Prof, Dept of ECE Pragati Engg College, Surampalem, V. N. M. Brahmanandam. K| Asst.Prof, Dept of ECE, M Tech Scholar,Asst.Prof, Dept of ECE Pragati Engg College, Surampalem
Keywords
Related Articles
- EP ID EP16239
- DOI -
- Views 413
- Downloads 19
Effective Stint Harmonisation For Mobile In Marine Sensor Networks
Deploy underwater sensors to record data during the monitoring mission, and then recover the instruments. This approach has the problems on Real time monitoring is not possible. No interaction is possible between ons...
Harmonics Reduction of a Single Phase Half Bridge Inverter
This paper displays a way to deal with minimize the sounds contained in the output of a solitary stage half scaffold inverter. With a perspective to decreasing Harmonic a LC low pass filter is utilized which hinders...
Prevention of Sensitive Information by Enhancing Cloud Access Control
the scheme prevents replay attacks and supports creation, modification, and reading data stored in the cloud. We also address user revocation. Moreover, our authentication, and storage overheads are comparable to cen...
New Topology For Hybrid Wind-Solar Energy System
Preventing Environmental pollution is becoming a tough task to the scientist. This paper presents a new system configuration which allows the two sources to supply the load separately or simultaneously depending on t...
We introduce the Contributory Broadcast Encryption (ConBE) primitive, which is a half and half of GKA and BE. Contrasted with its preparatory Asiacrypt, this gives complete security proofs, outlines the need of the a...