A Substrate Biased Full Adder Circuit
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 3
Abstract
With the recent advances in the VLSI design and technology, the challenge in the design complexity of IC has grown. One of the major challenges is to design logic with power minimization. This is due to two reasons; one is the long battery backup for mobile and portable devices and second is due to increase in number of transistors packed in a single chip which will lead to reliability problems. As addition is one of the indispensible operations in digital system we selected the basic full adder and the substrate biased full adder. The design criterion of a full adder is usually multi – fold. In this paper we did a comparative study based on the number of transistor used. The circuits are simulated in a famous EDA tool ORCAD. The results show that there is a considerable reduction in transistor count with respect to substrate biasing. In future these adders can be developed into an enhanced ALU with added features.
Authors and Affiliations
C. Saravanakumar
Keywords
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- EP ID EP19894
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