A Survey of Metastability Errors in CMOS Digital Circuits

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A Survey of Metastability Errors in CMOS Digital Circuits

Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 1

Abstract

Recent advances in complementary metal oxide semiconductor (CMOS) technology have led to unparalleled levels of integration in digital logic systems. By and large, these digital logic systems require a clock to synchronize signals and ensure proper operation. Due to the path propagation delay and clock synchronization setup hold time failure errors are occurs in digital circuits. Depending upon the application, the errors are described by a number of different terms including “synchronization failure,” “arbitration error,” and “metastability error.” The underlying mechanism for all of these problems is the same, and of these terms, “metastability error” is the most general because it describes the failure of the element within the circuit and not the application. Metastability is a widespread phenomenon and errors may occur in any synchronous circuit where an input signal can change randomly with respect to a reference signal. The reference signal may be either a voltage based reference, such as a bias voltage, or a time based reference, such as a clock signal.

Authors and Affiliations

Manisha Thakur , Puran Gaur , Braj Bihari Soni

EP ID EP141333
DOI -
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