A Systolic Hardware Architecture of Montgomery Modular Multiplication for Public Key Cryptosystems

Abstract

The Montgomery modular multiplication is mostly used in the field public-key cryptosystems. This work presents how to relax the data dependency in conventional word-based algorithms to increase the possibility of reusing the current words of variables. With the greatly relaxed data dependency, i proposed a novel scheduling scheme to alleviate the number of memory access in the developed scalable micro architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost 1=ðw _ 1Þ times that of conventional scalable architectures. The proposed one also retains a latency of exactly 1 cycle between the operations of the same words in 2 consecutive iterations of the Montgomery modular multiplication algorithm when employing enough processing elements. To Compared to the design with previous work, experimental results shows that the proposed one achieves an 55 percent reduction in power consumption with no degradation in throughput. The number of reduced memory access not only leads to lower power consumption, it also facilitates the design of scalable architectures for any precision of operands.

Authors and Affiliations

Vinoth Kumar. D, Senthilkumaran. V

Keywords

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  • EP ID EP23768
  • DOI http://doi.org/10.22214/ijraset.2017.4061
  • Views 271
  • Downloads 7

How To Cite

Vinoth Kumar. D, Senthilkumaran. V (2017). A Systolic Hardware Architecture of Montgomery Modular Multiplication for Public Key Cryptosystems. International Journal for Research in Applied Science and Engineering Technology (IJRASET), 5(4), -. https://europub.co.uk/articles/-A-23768