A Wide Range All Digital Feedback Duty Cycle Corrector
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 4
Abstract
This concise presents a Modified Successive Approximation Register (MSAR)-based duty cycle corrector (DCC), which achieves low jitter, fast lock time with an accurate 50% duty cycle correction. This Modified SAR adopts a binary search method to condense lock time while maintaining tight synchronization between effort and production clocks. The projected DCC consists of a duty-cycle detector, a duty-cycle adjuster, MSAR controller. In order to obtain fast duty-correction with a tiny die region, a MSAR-controller is demoralized as a duty-correction controller. A modified successive approximation register-controller reduces the locking time and allows the DCC to follow the process, voltage, temperature, and load variations (PVDL). The MSARDCC circuit has been implemented in a 0.18- μm CMOS process which corrects the duty rate within 5 cycles which has a closed loop characteristic. The measurement power dissipation and area occupation are 5581nW and 0.033mm2 respectively.
Authors and Affiliations
K. Sindhuja , C. Pandiarajan
Keywords
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