Advanced Low Power CMOS Design to Reduce Power Consumption in CMOS Circuit for VLSI Design
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 7
Abstract
Low power has emerged as a principal theme in today's electronic industry. Energy efficiency is one of the most critical features of modern electronic systems designed for high speed and portable applications. Reduction of power consumption makes a device more reliable and efficient. The minimum amount of power consumption was a major driving force behind the development of CMOS technologies. As a outcome, CMOS technology are best known for low power consumption devices. However, for minimizing the power consumption of system or device, simply knowing that CMOS devices may consume less power than equivalent devices from other technologies does not help much. It is important to know not only how to calculate power consumption, but also to calculate how various factors such as input voltage level, input rise time, source leakage current, Gate current, Switching power, short-circuit power, power-dissipating capacitor, and output loading affect the power requirement of a device. This paper presents an energy efficient and eco-friendly technique for overcoming power consumption in CMOS devices, focusing on calculation of power-dissipation in various components and, finally, the determination of various ways to reduce the total power consumption in a CMOS device. This technique has less power dissipation when compared to the conventional CMOS design style also the proposed technique is advantageous in many of the low power digital circuit design applications.
Authors and Affiliations
Pramoda N V
Keywords
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