AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN
Journal Title: International Journal on Computer Science and Engineering - Year 2011, Vol 3, Issue 9
Abstract
Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using several adiabatic logic styles, which are derived from static CMOS logic, without a large change. The full adders are designed using 180nm technology parameters provided by predictive technology and simulated using HSPICE. The full adders designed are compared in terms of average power consumption with different values of load capacitance, temperature and input frequency. The different designs of full adder are also compared on the basis of propagation delay exhibit by them. It is found that, full adders designed with adiabatic logic styles tends to consume very low power in comparison to full adder designed with static CMOS logic. Under certain operating conditions, one of adiabatic designs of full adder achieves upto 74% power saving in comparison to the full adder designed with static CMOS logic.
Authors and Affiliations
Praveer Saxena , Prof. Dinesh Chandra , Sampath Kumar V
Keywords
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