An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2017, Vol 8, Issue 2
Abstract
One of the fundamental requirements of real time operating systems is the determinism of executing critical tasks and treating multiple periodic or aperiodic events. The present paper presents the hardware support of the nMPRA processor (Multi Pipeline Register Architecture) dedicated to treating time events, interrupt events and events associated with synchronization and inter-task communication mechanisms. Because in real time systems the treatment of events is a very important aspect, this paper describes both the mechanism implemented in hardware for prioritizing and treating multiple events, and the experimental results obtained using Virtex-7 FPGA circuit. The article's element of originality is the very short response time required in treating and prioritizing events.
Authors and Affiliations
Ionel ZAGAN, Nicoleta Cristina GAITAN, Vasile Gheorghita GAITAN
Keywords
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- EP ID EP249028
- DOI 10.14569/IJACSA.2017.080206
- Views 61
- Downloads 0
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