Abstract

Network-on-chip (NoC) designs are based on a compromise among the most important elements viz. power dissipation, latency and the balance is usually defined at design time. In the research work we have used Efficient Rank Based fault-tolerant deflection routing (FTDR) algorithm to tolerate faults. The research is intended to reduce the router area by avoiding the table based routing path computation. The Efficient Rank Based algorithm has been proposed in the research to reduce the area and the power consumption of the overall Network on Chip. For Rank-Based fault tolerant deflection routing we provide a particular rank to our routers according to our NoC routing path(s). It does not require routing table to update completed path and switching path.

Authors and Affiliations