An Enhanced Area Reduction Technique for Integrated Circuit using Genetic Algorithm
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2014, Vol 16, Issue 2
Abstract
Genetic algorithms are implemented as a computer simulation in which a population of abstract representations (called chromosomes or the genotype or the genome) of candidate solutions (called individuals, creatures, or phenotypes) to an optimization problem evolves toward better solutions. In this paper Genetic Algorithm has been implemented to reduce the area for integrated circuits. Different operators have been implemented along with the proposed algorithm for area reduction of integrated circuits. It has been found that the proposed algorithm gave better results as compared to other operators in order to minimize the area. Genetic algorithm with proposed operator uses the least CPU time and the least number of iterations to reduce the area of integrated circuit
Authors and Affiliations
Mr. Amarjit Singh
Keywords
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- EP ID EP121374
- DOI 10.9790/0661-16211419
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