AN IMPLEMENTATION OF BYPASSING BASED MULTIPLIER BY USING INCREMENTAL ADDER
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 5, Issue 4
Abstract
In the recent growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. Hence it is very important for modern DSP systems to design high speed multipliers. Based on the simplification of addition operations in a bypassing multiplier, a multiplier by using incremental adder is proposed. Compared with row bypassing multiplier, column bypassing multiplier and 2-dimensional bypassing multiplier, our proposed multiplier reduces the number of computations and increases the speed.
Authors and Affiliations
A. Haritha
Keywords
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- EP ID EP95964
- DOI 10.5281/zenodo.48823
- Views 91
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