An Optimal Design of UP-DOWN Counter as SAR Logic Based ADC using CMOS 45nm Technology
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 4
Abstract
In this paper an analog to digital converter architecture is introduced. The proposed design is based on Up-Down counter approach SAR type ADC. This design offers less design complexity which leads to low power consumption. Based on the proposed idea, a 4-bit ADC is simulated in Microwind 3.5 environment using 45nm CMOS technology with supply voltage of 1 V. The ADC is designed with control signal like Start of conversion (SOC) and End of conversion (EOC). The ADC design consumes 3.2mW of power. The proposed ADC design is optimized to area of 829.6µm2.
Authors and Affiliations
Miss. Rohini Mane, Prof. Swati Shetkar
Keywords
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- EP ID EP391051
- DOI 10.9790/9622-0704063640.
- Views 109
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