Area and Power Efficient MSIC Test Pattern Generation for BIST
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 5
Abstract
This paper proposes a technique to generate the multiple test patterns varying in single bit position for built-in-selftest (BIST). The conventional test patterns generated using LFSR have an absence of correlation between consecutive test vectors. So, in order to improve correlation between the subsequent test vectors, test patterns were produced using binary to thermometer code converter. The methodology for producing the test vectors for BIST is coded using VHDL and simulations were performed with ModelSim 10.0b. 100% fault coverage is achieved with less number of test patterns. The Area utilization, power and delay report were obtained with Xilinx ISE 9.1 software. The area reduction of 62%, power reduction of 13% is achieved while generating test patterns using binary to thermometer code converter when compared with the patterns generated using Reconfigurable Johnson counter and LFSR.
Authors and Affiliations
M. Nandini Priya, Dr. (Mrs. ) R. Brindha
Keywords
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- EP ID EP20419
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