Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2014, Vol 10, Issue 10
Abstract
To perform fast addition operation, CSLA is one of the fastest adders used in many data-processing processors. Analyzing the structure of Regular CSLA (R-CSLA) and Modified CSLA (M-CSLA), there is a scope to reduce the area further. This work uses a simple gate level modification and a modified XOR gate is proposed to be used in the circuit. Based on this modification, 16-bit Area Efficient CSLA (AE-CSLA) is designed which provides 32% reduction in area when compared with R-CSLA and 12.5% reduction in area when compared with M-CSLA. This work is implemented in CADENCE VIRTUOSO using 180nm CMOS process technology.
Authors and Affiliations
Gagandeep Singh , Chakshu Goel
Keywords
Related Articles
- EP ID EP147313
- DOI -
- Views 133
- Downloads 0
Application of Least Squares Parameter Estimation Techniques in Fault Detection
Failure detection has been the subject of many studies in the past. Modern technology has required highly complex dynamic systems. A critical system is any system whose ‘failure’ could threaten the system’s environ...
Improved Transformerless Inverter for PV Grid Connected Power System by using ISPWM Technique
This paper presents an improved transformerless inverter with common mode leakage current elimination for a photovoltaic grid connected power system by using inverse sine carrier pulse width modulation (ISPWM). To...
Network Monitoring and Analysis by Packet Sniffing Method
Today we are seeing that computer networks are increasing in their sizes very rapidly. Number of its user increased in past few years and traffic flows in networks also increased, so it’s very important to monitor...
Comparison of Current Modes in CMOS Analog Multipliers
A study and comparison between current mode CMOS analog multiplier, ±1.5 V High frequency four quadrant current multiplier and ±1.2 V High frequency four quadrant current multiplier has been carried out in this pap...
Channel Capacity Analysis of MIMO System in Correlated Nakagami-m Fading Environment
We consider Vertical Bell Laboratories Layered Space-Time (V-BLAST) systems in correlated multiple-input multiple-output (MIMO) Nakagami-m fading channels with equal power allocated to each transmit antenna and also we c...