Asynchronous Viterbi Decoder Using Four Phase Handshake Protocol
Journal Title: International Journal of Engineering and Science Invention - Year 2017, Vol 6, Issue 12
Abstract
In this paper design of asynchronous Viterbi decoder is shown. Various protocols can be use to design asynchronous digital system. Bundle data protocol is one of them which are being used here to design decoder. Asynchronous Viterbi decoder for code rate ½ and constraint length 3 is designed using Xilinx 13.1. Four phase bundled data protocol is used because of its simplicity of designing to reduce the dynamic power of decoder. Register exchange method is well known method used for the design of Viterbi decoder. Here results are compared with the two different methods of decoder design. Hybrid register exchange method is being outperforms than register exchange method as this helps in reducing switching activity and hence the dynamic power. Proposed HRE method helps to reduce average dynamic power by 16.95% than proposed RE method designed using four phase handshaking protocol. XPower analyzer tool of Xilinx13.1 is used to calculate the dynamic power.
Authors and Affiliations
Mr. Girish D. Korde, Dr. Sanjay L. Haridas
Keywords
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