[b][i]Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique[/i][/b]
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 11
Abstract
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it showsless computation and less complexity since it reduces the total number of partial products to half of it. This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design with new MGDI technique gives far better result in terms of area, switching delay and power dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result shows great improvement in terms of area, switching delay and power dissipation.
Authors and Affiliations
Nitin Singh , M. Zahid Alam
Keywords
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