BISR SCHEME USING BENCH MARK TESTING SEQUENTIAL CIRCUIT S27

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BISR SCHEME USING BENCH MARK TESTING SEQUENTIAL CIRCUIT S27

Journal Title: GRD Journal for Engineering - Year 2016, Vol 1, Issue 0

Abstract

In this bench mark testing sequential circuit S27 is tested by using Built in Self Repair concept. This paper describes an on-chip test generation method for functional broadside tests. The hardware is based on the application of primary input sequences initial from a well-known reachable state, therefore using the circuit to produce additional reachable states. Random primary enter sequences are changed to avoid repeated synchronization and thus differed various sets of reachable states. Functional broadside tests are two-pattern scan based tests that avoid over testing by ensuring a circuit that traverses only reachable states in the functional clock cycles for a check. This consist of the input vectors and the equivalent responses. They check the proper operation of a verified design by testing the internal chip nodes. This test is useful to cover a very high percentage of modeled faults in logic circuits and their generation is the main topic of this method. Often, functional vectors are understood as verification vectors, these are used to verify whether the hardware actually matches its specification. Though, in the ATE world, any one vectors applied are understood to be functional fault coverage vectors applied during developing test, then the fault coverage area easily detected. This paper shows S27 circuit is used in Multiplier Circuit for Testing Application and it is done by Verilog Programming and simulated by Modalism 6.5version and Synthesis by Xilinx Tool

Authors and Affiliations

R. N. Nivethitha, Dr. A. Kaleel Rahuman

Keywords

EP ID EP303137
DOI -
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