Built-In Self-Repair Techniques of Embedded Memories with BIST for Improving Reliability
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2019, Vol 21, Issue 1
Abstract
Error correction code (ECC) and built-in selfrepair(BISR) techniques by using redundancies have beenwidely used for improving the yield and reliability of embeddedmemories. The target faults of these two schemes are soft errorsand permanent (hard) faults, respectively. In recent works, thereare also some techniques integrating ECC and BISR to deal withsoft errors and hard defects simultaneously. However, this willcompromise reliability, since some of the ECC protection capabilityis used for repairing single hard faults. To cure this dilemma,we propose an ECC-enhanced BISR (EBISR) technique, whichuses ECC to repair single permanent faults first and sparesfor the remaining faults in the production/power-ON test andrepair stage. However, techniques are proposed to maintain theoriginal reliability during the online test and repair stage. We alsopropose the corresponding hardware architecture for the EBISRscheme. A simulator is implemented to evaluate the hardwareoverhead (HO), repair rate, reliability, and performance penalty.Experimental results show that the proposed EBISR scheme canimprove yield and reliability significantly with negligible HO andperformance penalty.
Authors and Affiliations
P. S. N. Bhaskar M, B. Sarada M, Kandregula Shailajam
Keywords
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- EP ID EP434817
- DOI 10.9790/0661-2101010815.
- Views 81
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