Comparison of Power and Delay in Different Types of Full Adder Circuit
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 11
Abstract
In this review paper 1-bit CMOS full adder cells are studied using standard static CMOS logic style. The comparison is carried out using several parameters like number of transistors, delay, power consumption and power delay product (PDP).The circuits are designed at transistor level using 32nm CMOS technology. Different full adders are studied in this paper like Transmission gate (TGA) ,Static energy recovery factor (SERF),Gate Diffusion Input full adder (GDI), 14 T full adder using XNOR/XOR cell, 8 T full adder using 3 T XNOR gate.
Authors and Affiliations
N. Sabari Manoj, K. Suriya
Keywords
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- EP ID EP22830
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