Configuration as well as Performance of an On-Chip IncarnationArrangement for Multiprocessor System-On-Chip
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2015, Vol 3, Issue 7
Abstract
The novel on-chip coordinate in silicon indicated course of action to fortify ensured development change in multiprocessor SOC applications. A pipelined circuit-exchanging Employed in the proposed structure with FIFO strategy converged with a multistage system topology in segment way setup game plan. The runtime course strategy connected with by part way setup plan for subjective development changes adjacent the Error Correction Block (ECB). The circuit-exchanging technique offers the permuted information and its humbler overhead draws in the upside of stacking various structures in framework on chip. A CMOS test-chip with 0.13m insists the sound judgment and gainfulness of the proposed outline. The indicated exploratory result in the proposed on-chip system accomplishes 1.9x to 8.2x diminishment of silicon overhead emerged from other setup approaches.
Authors and Affiliations
Badita Kali Vara Prasad| Dept of ECE K L University, Green Fields, Vaddeswaram, Guntur (DT), JeswanthThezaNadella| Dept of ECE K L University, Green Fields, Vaddeswaram, Guntur (DT)
Keywords
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- EP ID EP16506
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