Defeating scan based attacks on secure AES with on-chip comparison
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 2
Abstract
Hardware implementation of Advanced Encryption Standard (AES) algorithms is subject to various attacks. The scan chains introduced for hardware testability open a back door to potential attacks. Here, a scan-protection scheme that provides testing facilities both at production time and over the course of the circuit’s life are proposed .The underlying principles to scanin both input vectors and expected responses and to compare expected and actual responses within the circuit. Security of AES is achieved with use of Secure Comparator and Secure Comparator with Masking. Instead of directly shifting DUT’s responses (Sout) out of the chip, the ATE also provides the expected response using the Sexp pin and the actual test response is on-chip compared with the expected one. After having compared all #SFF bits captured in the scan chain, the signal TesRes is asserted. Compared to regular scan tests, this technique has no impact on the quality of the test or the model-based fault diagnosis. It entails negligible area overhead and avoids the use of an authentication test mechanism.
Authors and Affiliations
Vasanthidevi. P , Sabareeswari. T. C
Keywords
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