Design a P arallel P ipeline Radix - 4 FFT Architecture
Journal Title: International Journal of Scientific Research and Management - Year 2014, Vol 2, Issue 10
Abstract
This paper presents a novel design to develop parallel pipelined architectures for the fast Fourier transform (FFT). The architecture is based on the radix - 4 algorithm. By exploiting the regularity of the algorithm, butterfly operation and multiplier modules were designed. The architecture adopts four butterflies, and the pipeline stage is optimized to b alance the processing speed and the area. Novel parallel pipelined architectures for the computation of complex and real valued fast Fourier transform are derived
Authors and Affiliations
Amaresh Kumar
Keywords
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- EP ID EP214222
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