Design a pattern generator with low switching activity to test complex combinational logic with high test coverage
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 4
Abstract
In circuit large number of combinational logic used so logic depth is large, so it is impossible to test every fault with other techniques because it’s take more time. In order to increase speed of an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. To solve this problem an Automatic Test Pattern Generator (ATPG) is proposed based on modification of FAN (fan-out-oriented test generation algorithm) Algorithm is describe. Also with some techniques reduce the switching activity of generated patterns for decrease the power consumption of ATPG.
Authors and Affiliations
Jay Bharatbhai Dabhi
Keywords
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