Design & Implementation of 64 bit ALU for Instruction Set Architecture & Comparison between Speed/Power Consumption on FPGA  

Abstract

In the present paper design of 64 bit ALU is presented. Arithmetic Logical Unit is the part of Microprocessor. All the arithmetic & logical functions are performed inside the ALU. So ALU is the heart of the microprocessor.The speed of the ALU decides the speed of the microprocessor. Now in MOS Technology the power consumption is depend upon then switching frequency of the clock as P=CV2 f Here P is the power consumption C is the capacitance of the interconnections f is the clock frequency of the design So if the clock frequency is reduced then the power consumption is less but on the other side of the coin the speed (performance) is reduced at a significant amount.So we should choose a architecture so that when no instruction is available to ALU it is transferred in power down mode i.e during the waiting states no power is consumed by the ALU.ALU is the part of the instruction set architecture defined the microarchitecture of the processor. The processor architecture is defined by the instruction set.  

Authors and Affiliations

1Rajeev Kumar , 2Manpreet Kaur

Keywords

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  • EP ID EP93636
  • DOI -
  • Views 82
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How To Cite

1Rajeev Kumar, 2Manpreet Kaur (2012). Design & Implementation of 64 bit ALU for Instruction Set Architecture & Comparison between Speed/Power Consumption on FPGA  . International Journal of Advanced Research in Computer Engineering & Technology(IJARCET), 1(4), 186-193. https://europub.co.uk/articles/-A-93636