Design analysis of CNTFETs based Full Adder using CVSL
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 11
Abstract
In this paper, the design analysis, implementation and comparison of different types of full adders is done. The adders being a very important basic logic functional block are required in many complex and high end circuits. Also with the growing trend for nanotechnology, it has become mandatory to reduce the circuit size at every possible step. One such initiative is the adoption of the carbon nanotubes as these have size very small as compared to the Silicon based CMOS transistors. Also when these nanotubes are implemented along with the cascade voltage switch logic, the result is as desired. In this research work, full adder circuits are designed and implemented using different channel material and logics. The circuits designed are the Full Adder using CMOSFETs that use the Silicon substrate as the channel material and Carbon nanotubes based Full adder that uses the Carbon nanotubes field effect transistors. Both the circuits are implemented using the cascade voltage switch logic. These circuits are compared with the standard library Full adder using delay, power consumption, and transistor count as the parameters for comparison. It was found that the CNTFETs based Full adder using CVSL is more efficient with 50% less power consumption and 48.9% less delay when compared with CMOS based full adder that too using the CVSL.
Authors and Affiliations
Mitali Sharma, Dr. Rajesh Mehra
Keywords
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- EP ID EP392841
- DOI 10.9790/9622-0711040106.
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