Design and analysis of 16-bit Full Adder using Spartan-3 FPGA
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 7
Abstract
In ALU, adders plays an important role in arithmetic operations. Depending on the application, n-Bit adders to be designed like 8-bit, 16-bit, 32-bit and etc. Design of High-Speed adders is real challenge, especially in Semi-Custom designs, because the technique that is used in the design of various n-bit adders is different. In ALU, the use of ripple-carry adder takes most of the time in addition. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look-a-head adder. This paper presents the design and implementation of 16-bit adder by using 4-bit CLA. Here the most powerful ECAD tool VHDL is used for design and analyzed with SPARTAN-3 FPGA. The analysis is taken place in between VHDL primitive 4-bit adder and VHDL design of 4-bit CLA. Finally the result is concluded.
Authors and Affiliations
B. N. Srinivasa rao , R. Prasada rao
Keywords
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