Design and Analysis of Low Power High Speed Current Latch Sense Amplifier
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 5
Abstract
This paper is about the comparison of the conventional CLSA and a current latch sense amplifier with body bias controlled CLSA. In late, used for speed up of the precharging time of Sense Amplifier. The CLSA is capable of high-speed precharging with little increase in transistors counts. We will also verify the various result like Power consumption, Offset Voltage and noise margin at 180 nano meter technology. Here in this Paper we will see that when Vdd increases circuit the ability to avoid the noise increases but power consumption are increases. Simulation result shows that speed of Sense Amplifier are increased by 11% at same time the power dissipation reduced by 80%.
Authors and Affiliations
Jyoti Sharma, Rajesh Parihar
Keywords
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- EP ID EP20626
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