Design and Implementation of an Ultra-Low Power High Speed CMOS Logic using Cadence

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Design and Implementation of an Ultra-Low Power High Speed CMOS Logic using Cadence

Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 5

Abstract

DMTGDI is introduced an ultra-low power, high speed dual mode cmos logic family. It mainly improves characteristics of gate diffusion sub-threshold circuit design. A dmtgdi of type a and type b design was implemented in cmos logic circuits and the proposed configuration was employed in a single bit full adder was implemented in 10t configuration to analyses the performance through the simulations. During the simulation minimum delay was obtained with the help of proposed dmtgdi technique and its consume the minimum amount of power. In dmtgdi 60% performance improvement has been done in over conventional dml, and significant reduces power-delay product (pdp), both in dynamic mode, static mode 95%, and 75% respectively. Layout simulation performance is done in single bit adder. Tgdi gates are implemented additionally because this is the previous version of dmtgdi. The proposed architecture was implemented in cadence virtuoso with 180nm width of cmos logic and the post simulation was obtained through asura.

Authors and Affiliations

L. Vasanth, D. Yokeshwari

Keywords

EP ID EP24167
DOI -
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