Design And Implementation of CMOS Adder Cell With Reduced Leakage Power Technique In 90nm Technology
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 9
Abstract
Now-a-days Power consumption (or) power dissipation has becomes the most important criteria for implementing anyone of the digital circuit. While calculating the efficient value of the output of that particular digital circuit, we may use the concept of scaling. But, while increasing the scaling process there may be a loss of leakage current. Due to the leakage current the usage of power (power dissipation) is increased. For removing these kinds of leakage currents we are going to use “power gating techniques”. The adder cells mainly focus on reduction of power and increasing of speed. For mobile applications, designers work within a limited leakage power specification in order to meet good battery life. The designers apart from leveling of leakage current to ensure correct circuit operation also focuses on minimization of power dissipation. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper will focus on reducing sub threshold leakage power consumption and ground bounce noise during the sleep to active mode transition. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. We will perform analysis and simulation of various parameters such as standby leakage power, active power, ground bounce noise and propagation delay using Cadence Spectre 90nm standard CMOS technology.
Authors and Affiliations
J Manohar, Ch. Janardhan, K. V. Ramanaiah
Keywords
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