Design and Implementation of Efficient Modulo 2n+1 Adder
Journal Title: International Journal of Computational Engineering and Management IJCEM - Year 2014, Vol 17, Issue 6
Abstract
In this brief, we proposed an efficient weighted modulo (2n +1) adders. This is achieved by modifying existing diminished-1 modulo (2n +1) adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n − 1} produced by existing diminished-1 modulo (2n +1) adders. And our proposed adder gives better performance in terms of area and power when compared with previously existing architectures. We have implemented the proposed adders using 0.18-µm technology, and also compared the performance parameters of those adders.
Authors and Affiliations
V. Jagadheesh, Y. Swetha
Keywords
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