Design and Implementation of FPGA Based MIMO Decoder in Wireless Receiver
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2012, Vol 1, Issue 7
Abstract
This paper address the implementation of Multi-Input-Multi-Output (MIMO) Decoder using FPGAs embedded in a prototype of Wireless Communication receiver. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free from interference, from which to estimate the transmitted symbols. The MIMO system-Encoder and decoder is part of a multi-carrier code division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link that is able to handle up to 32 users and provides high transmission bit-rate. The main motto of this is to design the FPGA based MIMO Decoder. To demonstrate this, MIMO Encoder is also included in this project. The Data links for Two symbol period were established and found that the MIMO decoder outputs follows the MIMO Encoder input. We report results using FPGA devices of the Xilinx family.
Authors and Affiliations
Pravin Wasudeorao Raut, Dr. S. L. Badjate
Keywords
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- EP ID EP27505
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