Design and Implementation of FPGA Radix-4 Booth Multiplication Algorithm
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 9
Abstract
Fast multipliers are essential parts of digital signal processing systems.The system performance is based on the performance of multiplier used in the system, because it is the slowest component among all components used. One of the major design issue is optimizing speed and area of the multiplier which are two conflicting constraints. Hence realization of high speed multipliers is done to enhance parallelism and to decrease the number of calculation stages. For high speed arithmetic logics, a new architecture called Radix -4 Booth Multiplication algorithm which is based on MAC logic have been designed and implemented on Xilinx FPGA device. It is a combination of multiplication with accumulation and a hybrid adder(CSA and CLA) is designed to improve system performance. Here, multiplication is done as the series of repeated addition by generating partial products and finally adding them. The modified Booth Algorithm is used to reduce the number of partial products generated by a factor of 2. The multiplicand is considered as the number to be added and the multiplier is the number of times that it is added, and the result is the product.
Authors and Affiliations
A. Rama Vasantha, M. Sai Satya Sri
Keywords
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